module ALUcontrol(
    input logic [3:0] ALUctr,
    output logic SUBctr,
    output logic SIGctr,
    output logic [1:0] OPctr
    );
    
    logic [3:0] control;
    assign {SUBctr,SIGctr,OPctr}=control;
    always_comb
        case (ALUctr)
            4'b0000:control<=4'b0000;//add
            4'b0010:control<=4'b1111;//slt
            4'b0011:control<=4'b1011;//sltu
            4'b0110:control<=4'b0001;//or
            4'b1000:control<=4'b1000;//sub
            4'b1111:control<=4'b0010;//srcB
            default:control<=4'bxxxx;
         endcase
endmodule
